1. Field of the Invention
The invention relates to self-resetting CMOS (SRCMOS) circuitry and more particularly to sense amplifiers used in the receipt of signals from a memory or other device.
2. Description of Related Art
Sense amplifiers are typically used in receiving data over a data bus, typically from a memory or the like, where the signal level is relatively low compared to the signal level used internal to the processor. SRCMOS sense amplifiers are known and in use in the industry. One problem associated with the use of SRCMOS sense amplifiers is the delay introduced by the sense amplifiers due to the fact the data is typically processed through two or more stages and the sense amplifier cannot receive new data signals until previously received data signals have been properly amplified and transmitted to other circuitry within the processor. The prior art SRCMOS sense amplifiers typically consist of three stages, an input stage, a buffer stage and an output or driver stage. In SRCMOS circuitry, the circuits must be reset before additional data can be received. However, the reset must not occur until after the output signals of the sense amplifier circuit have been properly recorded in another circuit within the processor. The reset is performed by charging input gates to a high level, one of which is typically discharged to the memory cell to indicate a signal presence. A certain amount of time is required for this discharge. This reset and discharge tends to introduce undesirable delay.
SCRMOS sense amplifier circuitry is typically reset by means of one or more reset pulses generated by a reset chain which is activated when the input data has reached the output of the amplifier circuit. One way to increase the hold time of the data within the circuit, thereby assuring that there is sufficient time for data to be recorded in a receiving circuit, is to lengthen the delay of the reset chain. A drawback, however, of this technique is that lengthening of the reset chain delay also lengthens the cycle time of the sense amplifier thereby introducing a delay. Such a delay reduces the effective data processing capability of the processor.